1. Field of the Invention
This invention relates generally to superconductive memory cells wherein information is stored in the cells in the form of at least a single circulating current. More specifically, it relates to memory array configurations which avoid a spurious half-select condition in unselected cells of the memory array. Still more specifically, it relates to superconductive memory cells wherein binary information is stored in a storage loop in the form of one or two circulating currents by the switching of at least a single storage device disposed in the storage loop. Still more specifically, it relates to superconductive memory cells wherein means are connected to the memory cells for applying at least a control magnetic field to only a selected one of the memory cells simultaneously with the application of an enabling current in the storage device of the storage loop. In some instances, the enabling current is diverted into a path, a portion of which is disposed in electromagnetically coupled relationship with the storage device, under control of a switchable device which diverts the enabling current into the path. In another instance, the memory cell storage loop is disposed in series in a path into which the enabling current is diverted and the diversion path is in parallel with a switchable device which itself is switched to divert the enabling current into its associated parallel path. In other instances, a current different from the enabling current is utilized to switch the storage device of a selected one of the memory cells. In these arrangements, either the enabling current or a separate current triggers a switchable device which diverts these currents into a path in parallel with the switchable device. This path has a portion disposed in electromagnetically coupled relationship with the storage device of the selected one of the memory cells which can switch when both the enabling current and a control magnetic field are encountered by the storage device of only the selected memory cell. In all the above-described arrangements, only the selected one of the memory cells encounters an enabling current and a control magnetic field which is sufficient to store information in the selected cell in the presence of a stored circulating current. Thus, the storage device of an adjacent memory cell in the same row encounters neither an enabling current nor a control magnetic field current. The storage device encounters, at most, a previously stored circulating current. Similarly, unselected cells in the same column of an array only encounter a half-select enabling current and possibly a circulating current, the sum of which are always well below the threshold current (I.sub.mo) of the storage gate. Thus all of the present arrangements avoid the situation where the combination of control magnetic field applied to more than one storage device (global) and stored circulating current can cause spurious switching of an unselected memory cell by applying control magnetic field to only one storage device (local).
1. Description of the Prior Art
The following patent and articles relate to superconductive memory cells which utilize at least a single storage device in a storage loop wherein binary information is stored in the form of at least a single circulating current. All of the memory cells shown utilize coincident current selection to store information and the coincident currents are applied in such a way that both selected and unselected cells encounter a control magnetic field (global). The memory cells of the present application are distinguishable over all the below-cited prior art inasmuch as only a selected one of the memory cells encounters a control magnetic field (local).
U.S. Pat. No. 3,626,391, Ser. No. 744,949, filed July 15, 1968 entitled "Josephson Tunneling Memory Array Including Drive Decoders Therefor" in the name of W. Anacker and assigned to the same assignee as the present application.
IBM Technical Disclosure Bulletin, Vol. 15, No. 2, July 1972, p. 449-451, "Memory Cell Using a Single Josephson Tunneling Gate," by W. Anacker.
IBM Technical Disclosure Bulletin, Vol. 15, No. 9, February 1973, p. 2904-2905, "NDRO Memory Cell Employing a Single Josephson Tunneling Gate," by W. Henkels.
IBM Technical Disclosure Bulletin, Vol. 16, No. 1, June 1973, p. 214, "Two-Junction Josephson Memory," by P. Wolf.
IBM Technical Disclosure Bulletin, Vol. 18, No. 11, April 1976, p. 3852-3855, "Josephson Feedback Memory Cells," by W. H. Henkels.